Virtual interconnections for reconfigurable logic systems
US5761484A · kind A · utility
305Cited by
16References
39Claims
0Family size
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Key dates
| Filing date | Sep 28, 1995 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Sep 28, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A compilation technique overcomes device pin limitations using virtual interconnections. Virtual interconnections overcome pin limitations by intelligently multiplexing each physical wire among multiple logical wires and pipelining these connections at the maximum clocking frequency. Virtual interconnections increase usable bandwidth and relax the absolute limits imposed on gate utilization in logic emulation systems employing Field Programmable Gate Arrays (FPGAs). A "softwire" compiler utilizes static routing and relies on minimal hardware support. The technique can be applied to any topology and FPGA device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.