System and method for reducing power consumption in high frequency clocked circuits
US5761517A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Aug 14, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method are provided which automatically change the output of an oscillator clock prior to its input to dynamic logic circuit elements as a system clock signal. The oscillator clock signal is controlled based upon a signal generated by a sensor which determines the power consumption of the integrated circuit. The frequency of the clocked signal is reduced (or increased) incrementally based upon the output of the sensor which detects the level of a specific circuit characteristic, relating to electrical power consumption. A pattern generator is used to input a digital signal to a series of interconnected registers which make up a loadable shift register. The output of the pattern generator is based upon the input from the sensor. The bits shifted through the shift register are ANDed with the oscillator clock signal to control the frequency of the system clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.