Method and apparatus for performing and operation multiple times in response to a single instruction
US5761524A · kind A · utility
5Cited by
4References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.