Rate based memory replacement mechanism for replacing cache entries when the cache is full
US5761716A · kind A · utility
19Cited by
12References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | May 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A rate based mechanism for determining which data to replace in a cache when the cache is full. The computer system processes data, which are associated with multiple channels or processes. These channels or processes have different, cyclic rates. When the cache is full, the system chooses the data to replace by selecting the data block in the cache that has the lowest rate and is the most recently used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.