Method and system for cache coherence despite unordered interconnect transport
US5761721A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1996 |
| Grant date | Jun 2, 1998 |
| Priority date | — |
| Expiry date | Jul 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0813
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for providing cache coherence despite unordered interconnect transport. In a computer system of multiple memory devices or memory units having shared memory and an interconnect characterized by unordered transport, the method comprises sending a request packet over the interconnect from a first memory device to a second memory device requiring that an action be carried out on shared memory held by the second memory device. If the second memory device determines that the shared memory is in a transient state, the second memory device returns the request packet to the first memory device; otherwise, the request is carried out by the second memory device. The first memory device will continue to resend the request packet each time that the request packet is returned.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.