Semiconductor memory device having an interconnect structure which improves yield
US5763908A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Jul 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
Abstract
A semiconductor memory device in which word lines are arranged so as to improve the yield with respect to bridging defects. The semiconductor memory device of the present invention has a plurality of interconnects arranged in parallel on a cell array portion, in which the interconnects are comprised of power lines and ground lines arranged alternately on the cell array portion, main word lines arranged on each side of the power lines, and a plurality of block word lines sequentially arranged between a single main word line and a ground line adjacent thereto and controlled by the main word line. In this way, interconnects are arranged in alternating groups so that interconnects having the same logic level during the standby mode are grouped together. The result of this arrangement is that interconnect bridges within a group will not lead to increased standby current, thereby substantially improving the yield of the semiconductor memory device. In addition, the spacing between groups of interconnects may be increased, further reducing the probability of increased standby current due to a bridging defect, thereby further increasing the yield.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.