Multi-stage symbol synchronization
US5764102A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1997 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Feb 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital communication receiver (#10) takes one complex sample (#20) of a baseband analog signal (#12) per symbol. A rectangular to polar converter (#44) separates phase attributes of the complex samples from magnitude attributes during coarse symbol synchronization (#28). A phase processor (#48) identifies clock adjustment opportunities which occur when relatively large phase changes take place between consecutive symbols. A magnitude processor (#46) influences symbol timing only during clock adjustment opportunities. The magnitude processor (#46) advances symbol timing in a phase locked loop when decreasing magnitude changes are detected during clock adjustment opportunities and retards symbol timing when increasing magnitude changes are detected during clock adjustment opportunities during coarse symbol synchronization (#28). A fine symbol synchronizer (#42) is used to refine coarse estimates of symbol synchronization in a data-directed manner (#82) by estimating incoming signal at sub-symbol intervals before and sampling instants to control oscillator (#22) in response to incoming signal estimates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.