Apparatus for reducing power consumption of device controlled by counter and noise due to counter reload
US5764108A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Oct 9, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing the power consumed by, and the noise generated at the output of a charge pump which is part of a phase locked loop circuit. A reduction in the power consumed by the charge pump is achieved by synchronizing the powering up of the charge pump bias circuit to the state of the counters which control the timing of the signal which triggers a charge pump cycle. In this way current is supplied to the charge pump circuit only when needed for the operation of the pump. A reduction in the noise present at the output of the charge pump caused by the reloading of the counters while the pump is activated is achieved by loading a portion of the counter bits prior to activating the pump. A circuit detects when the counter is close to a value of zero and produces a signal which loads the most significant bits of the counter. When the counter reaches a value of zero, the remaining bits are loaded. This reduces the number of counter bits which are loaded while the pump circuit is active, thus reducing the switching noise present on the pump output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.