Test structure and method to characterize charge gain in a non-volatile memory
US5764569A · kind A · utility
16Cited by
2References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 25, 1997 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Feb 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method and apparatus for charge gain characterization of non-volatile memory cells. The test structure of the present invention includes an array of non-volatile memory cells similar to that of the proposed product, but having the control gates of some or all of the cells of the array linked to form a common floating gate. In this way, charge leakage through any cell so linked will accrue in the common floating cell. Any such charge gain will be detectable through a variety of possible structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.