Semiconductor memory device and method of checking same for defect
US5764576A · kind A · utility
19Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Nov 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first test row decoder (9a) for selecting memory cells in normal rows in a test mode, a second test row decoder (9b) for selecting spare memory cell rows, a first test column decoder (10a) for selecting memory cells in normal columns, and a second test column decoder (10b) for selecting spare memory cell columns. A control circuit (11) may perform switching between four combinations of the row and column decoders by using a control signal (SRT) and a control signal (SCT). All spare memory cells are tested prior to reparation of a defective memory cell for yield enhancement.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.