Memory device and memory control circuit
US5764591A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Oct 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a memory element including a plurality of memory cells each designated by a row address signal and a column address signal, and a circuit for detecting a transition between the row address signal and the column address signal to thereby effect an equalize operation on the memory element. The supply of a row/column address signal including the row address signal and the column address signal to the memory element is cut off during a logical indeterminate period at the time of the transition. The row/column address signal immediately before its cutoff is held and the held signal is supplied to the memory element during the logical indeterminate period. Thus, a high-speed operation can be done by the equalize operation and the cutoff can provide the prevention of occurrence of a malfunction due to noise such as a glitch or the like.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.