Efficient address generation for convolutional interleaving using a minimal amount of memory
US5764649A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 29, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Mar 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/276
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A convolutional interleaving process which utilizes an addressing scheme that enables the amount of memory to be used in the convolutional interleaving process to be reduced is disclosed. A stream of data is convolutionally interleaved at a designated interleaving depth and a designated interleaving block length such that a first symbol in a designated block has an associated predetermined delay and each subsequent symbol in the designated block has a delay equal to more than its predecessor symbol. A plurality of delay related arrays, as well as an initial value array, a lower limit array, and an upper limit array, are calculated in order to define interleaving orbits. The convolutional interleaving process is accomplished by a convolutional interleaver which is arranged to take an incoming stream of data and output an interleaved stream of bits which is conceptually partitioned into blocks. A convolutional deinterleaving process, which is similar to the convolutional interleaving process is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.