Multi-byte processing of byte-based image data
US5764787A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/10016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Consecutive pixel values are loaded into the fields of a register. The data stored in the register is then transformed by operating on the register with one or more instructions that treat multiple pixel values as if they were single values. In a preferred embodiment, subsampled motion estimation processing is implemented on SIMD architecture. Values for consecutive pixels are loaded into the 8-bit fields of a SIMD register with a single byte-based SIMD load instruction. The contents of the register are then processed by applying one or more word-based SIMD instructions to the register which treat the data in the registers as 16-bit values. This word-based processing preferably results in sums of squares of differences between reference and target pixels used in motion estimation processing. Although the byte-based SIMD load instruction loads unwanted pixels (i.e., those pixels not selected for subsampled motion estimation processing) along with the desired pixels, the subsequent word-based SIMD processing treats the unwanted pixels as low-order bits of the desired pixels. The squares of differences may have errors, but the magnitudes of the errors are insignificant compared to the…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.