Method and system for selective serialization of instruction processing in a superscalar processor system
US5764942A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Aug 12, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method and system of the present invention permits enhanced instruction dispatch efficiency in a superscalar processor system capable of fetching an application specified ordered sequence of scalar instructions and simultaneously dispatching a group of the scalar instructions to a plurality of execution units on a nonsequential opportunistic basis. A group of scalar instructions fetched in an application specified ordered sequence on a nonsequential opportunistic basis is processed in the present invention. The present invention detects conditions requiring serialization during the processing. In response to a detection of a condition requiring serialization, processing of particular scalar instructions from the group of scalar instructions are selectively controlled, wherein at least a portion of the scalar instructions within the group of scalar instructions are thereafter processed in a serial fashion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.