Method and system for optimizing a critical path in a field programmable gate array configuration
US5764954A · kind A · utility
133Cited by
17References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1995 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a Field Programmable Gate Array ("FPGA") design system, a configuration is generated. A path of the configuration is selected as a critical path for optimization. The critical path is optimized by rerouting connections between the logical primitives of the critical path. Prior to the rerouting, the logical primitives of the critical path may be optimally placed within the FPGA configuration. Optimal performance of the critical path is thus achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.