Synchronization infrastructure for use in a computer system
US5764965A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Sep 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A synchronization backbone for use in a computer system having a system board containing at least one central processing unit for processing digital data, a memory coupled to the system board for storing the digital data, a plurality of subsystems, and a bus structure for transmitting electrical signals between the system board, the memory, and the plurality of subsystems. The synchronization backbone provides the infrastructure that enables professional quality synchronization between the various subsystems. A clock generator is used to generate a system clock that is transmitted to each of the subsystems. The sample rate of a designated subsystem is used as a digital synchronization signal. The selected digital synchronization signal is then transmitted to each of the other subsystems. A synchronization circuit adjusts the sample rates associated with the other subsystems according to the digital synchronization signal and the system clock. Synchronization may be achieve via the unadjusted system time, a media stream count, or a combination of the two.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.