Method and apparatus for optimizing PCI interrupt binding and associated latency in extended/bridged PCI busses
US5764996A · kind A · utility
19Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1995 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Nov 27, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method of implementing an enhanced PCI interrupt controller which accommodates the industry standard wire-or functionality. With such an arrangement a method and apparatus to identify a source of a PCI interrupt without the need for polling is implemented with a register-based architecture and staged initiator decode. The invention implements both the default industry standard and a non-polled (interrupt accelerator) mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.