Network controller which enables the local processor to have greater access to at least one memory device than the host computer in response to a control signal
US5765027A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 1994 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Sep 26, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/128
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An application specific integrated circuit (ASIC)/field programmable gate array (FPGA) which is a component of a wireless LAN controller including a local processor and a memory enables the controller to interface with both PCMCIA.TM. and AT.TM. host computer systems. The ASIC/FPGA enables communication between a radio frequency communication module, a local processor, and the host computer. The ASIC/FPGA also includes a throttle feature that decreases the access of the host computer in comparison to access of the local processor in order to enable the local processor to rapidly generate an acknowledge signal as required by various RF LAN specifications. During operation of the controller, data to be transmitted by the host computer onto the network is written by the host to an SRAM via the ASIC/FPGA, and the host commands the local processor via the ASIC/FPGA to forward the transmitted data to the RF communication module. Under the control of the ASIC/FPGA, the local processor then forwards the transmit data from the SRAM to the RF communication module. When data is received from the RF communication module, the local processor, under the control of the ASIC/FPGA, receives the dat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.