System and method of addressing distributed memory within a massively parallel processing system
US5765181A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1993 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Dec 10, 2013 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0692
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory location and a linearized index is assigned to each array element in an array. The processing element number of the processing element in which a particular array element is stored is computed as a function of a linearized index associated with the array element and a distribution specification associated with the array. In addition, a local memory address associated with the array element is computed as a function of the linearized index and the distribution specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.