Data processor with alocate bit and method of operation
US5765199A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1996 |
| Grant date | Jun 9, 1998 |
| Priority date | — |
| Expiry date | Sep 20, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/127
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor (10) has a cache array (40) and a control unit (58) for storing a number of recently accessed data lines. If an execution unit requests a data line that is not stored in the memory cache (a miss) then the control unit will request the data from an external memory device and allocate a location in the cache array in which it will store the requested data when returned. In the depicted embodiment, the control unit first attempts to allocate an invalid one of N possible locations, where N is the set way associativity of the memory cache. If none of the ways is invalid, then the control unit uses a least recently used (LRU) algorithm to select the location. Therefore, the data cache may be non-blocking up to N times to the same set.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.