Data processor with an efficient bit move capability and method therefor

US5765216A · kind A · utility

Assignee

• Motorola, Inc. · US

Inventors

• Chia-Shiann Weng · Austin, US
• Paul Astrachan · Austin, US
• Peter C. Curtis · Austin, US
• Donald C. Anderson · Austin, US
• Walter U. Kuenast · Austin, US
• Kenneth C. Weng · Austin, US

Key dates

• Filing date: Jun 17, 1996
• Grant date: Jun 9, 1998
• Expiry date: Jun 17, 2016

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F9/30167
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processor (40) includes source (60) and destination (61) address generation units (AGUs) to update source and destination addresses for efficient digital signal processing (DSP) functions. The data processor (40) includes an instruction decoder (41) which recognizes a bit movement instruction, which is frequently encountered in data interleaving operations. In response to the bit movement instruction, the instruction decoder (41) causes the source (60) and destination (61) AGUs to update their present addresses using variable offset values. The instruction decoder (41) further causes a bus controller (44) to convert these bit addresses to corresponding operand addresses and bit fields. The bus controller (44) accesses source and destination operands using the operand addresses. The instruction decoder (41) then causes an execution unit (45) to transfer a bit from the source operand indicated by the source bit field to a bit position of the destination operand indicated by the destination bit field.