Method of making a vertical integrated circuit

US5766984A · kind A · utility

Assignee

• Fraunhofer-Gesellschaft zur förderung der angewandten Forschung e.V. · DE

Inventors

• Peter Ramm · St. Catharines, CA
• Reinhold Buchner · Unterföhring, DE

Key dates

• Filing date: Sep 22, 1995
• Grant date: Jun 16, 1998
• Expiry date: Sep 22, 2015

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/975
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of making a vertical integrated circuit by providing first and second substrates surfaces of which have layers with circuit structures and metallization planes therein, by providing an etching mask on a primary surface of the first substrate, forming via holes in the first substrate extending through the masking surface and the layers of the first substrate, reducing the thickness of the first substrate from a surface opposite its layer surface, alignedly connecting the first substrate by its reduced surface to the layer surface of the second substrate, subsequent deepening of the via holes to the metallization plane of the second substrate and forming electrical interconnection between the metallization planes in the first and second substrates through the via holes.