Fabrication method for integrated circuits
US5767011A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Nov 14, 2016 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/923
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and resulting structure for fabricating interconnects through an integrated circuit. The method includes adding more power lines 80, 100, 151 and/or increasing the width of power lines 120 and/or adding a power bus 140 near regions of high current flow. The resulting structure also provides more metallization near regions of high current flow. Similar to the method, the resulting structure may include additional power lines 80, 100, 151 and/or wider power lines 120 and/or a power bus 140 to increase the amount of metallization. An improved routing technique is also provided. Such routing technique includes providing an initial Ucs value and then adding additional lines near high current regions to decrease the Ucs value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.