Pulse signal transfer unit employing post charge logic
US5767700A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Jun 27, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse signal transfer unit employing post charge logic, comprising a buffering circuit for transferring data with a specified logic value through a data transfer line, a PMOS transistor for supplying a voltage from a voltage source to the data transfer line to initialize a signal on the data transfer line, and a feedback loop circuit for applying the signal on the data transfer line to the PMOS transistor for one of the first and second time periods in response to an external write drive signal to control the PMOS transistor, the second time period being longer than the first time period. According to the present invention, in the case of accessing read data with a relatively narrow pulse width and write data with a relatively wide pulse width, the pulse signal transfer unit initializes the read data at a relatively high speed and the write data at a relatively low speed to provide a signal with a wider pulse width. Therefore, the pulse signal transfer unit is capable of preventing the formation of a current path and enhancing the data processing speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.