Noise insensitive high performance energy efficient push pull isolation flip-flop circuits
US5767716A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Sep 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An energy efficient D flip-flop circuit has a master latch, a slave latch and a push-pull circuit. This push-pull circuit includes an inverter having an input connected to the output of the master latch and a transmission gate clocked in a second phase having an input connected to the output of the inverter and an output connected to the output of the slave latch. This push-pull circuit speeds the C-to-Q delay time of the circuit because there is only one gate delay to output using this circuit. The master and slave latches may employ N-type MOSFETS, CMOS transfer gates or tri-state inverters in the feedback path. The master latch may employ a double pass transistor logic input. The push-pull circuit may employ a tri-state invertor in place of the inverter and transmission gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.