Distribution charge pump for nonvolatile memory device
US5767729A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Oct 31, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/12
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A distribution charge pump is disclosed that provides a high voltage output that can be used to write or erase EEPROM cells. The charge pump is enabled by a high (VCC) input signal, which is input to a pair of always-on pass transistors. The output of one of these pass transistors turns on a third transistor whose source is tied to an internal node that is coupled to one terminal of a MOS capacitor and the gate of a fourth transistor. The other terminal of the MOS capacitor is tied to a clock signal and the source and drain of the fourth transistor are tied respectively to the charge pump output and a high voltage power supply node (VPP). The capacitor stores charge on the internal node when the clock signal goes high and discharges when the clock signal goes low. Due to this discharge, the voltage at the internal node drops, which causes the third transistor to turn on and supply charge to the internal node, preventing the complete discharge of charges stored during the positive phase of the clock cycle. Therefore, the voltage at the first node rises over subsequent clock pulses. The fourth transistor turns on whenever the voltage at the first node is above threshold; thus the pum…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.