Pixel engine pipeline for a 3D graphics accelerator
US5767856A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Mar 15, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2360/121
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel engine pipeline (including a "front-end" and a "back-end") communicates pixel information between a graphics processor, a pixel engine, a data cache, and system memory. The "front-end" (for reading requested data) includes a command queue for receiving graphics instructions from a graphics processor. Read requests in the command queue are stored in a read request queue. Extraction instructions corresponding to at least a portion of the read request are stored in an attribute queue. Control logic determines whether the requested data is located in a data cache. The read request is stored in a load request queue and the requested data is retrieved from system memory into a load data queue, if the requested data is not in the data cache. The control logic stores the requested data into a read data queue. The requested data is provided to a stage of the pixel engine from the read data queue in accordance with the extraction instructions. A "back-end" (for writing graphics information to system memory) of the pixel engine pipeline includes a write data queue receiving write data from the pixel engine, wherein the write data includes pixel information interleaved with Z informati…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.