Layered circuit-board designing method and layered circuit-board
US5768106A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Jun 11, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01R12/523
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A layered circuit-board designing method and layered circuit-board where circuit-boards to be overlaid are connected at the center or an arbitrary position of each circuit-board. The layered circuit-board includes an upper-layer first circuit-board, a lower-layer third circuit-board, and an intermediate-layer second circuit-board between the first and third circuit-boards. A first connector is mounted on the first circuit-board, a second connector is mounted on the third circuit-board, a third connector is mounted on the top surface of the second circuit-board, while maintaining the positional relation between the third connector and the first connector, and a fourth connector is mounted on the bottom surface of the second circuit-board, while maintaining the positional relation between the fourth connector and the second connector. In addition, through holes are provided at pins of the third and fourth connectors for passing through the front and bottom surfaces of the second circuit-board.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.