Method of simulating AC timing characteristics of integrated circuits
US5768159A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | May 2, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of simulating AC timing characteristics at the pins of a device in of an application specific integrated circuit (ASIC) design is presented. The approach is fully automatic and is generalized, in the sense that both positive and negative Setup and Hold times and Propagation delays can be captured. The approach allows each bit of a data bus to be treated individually so as to be able to identify the worst case Setup time, Hold time and Propagation delay. Measurement is carried out in parallel for all data inputs and outputs. The need for manual intervention is eliminated and considerably reduces simulation time. Delay files are used through a call from a test bench, and the same testbench can be run on different delay information, namely pre-layout or post-layout delays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.