Method and apparatus for performing microprocessor integer division operations using floating point hardware
US5768170A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Jul 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for efficiently generating multiple integer quotients of integer numerators divided by a common integer denominator are implemented by multiplying a floating point approximation of the reciprocal of the integer denominator by floating point representations of the numerators, biasing the floating point quotients before rounding up or down as required. First, an initial approximation of the reciprocal of the denominator is computed (102) by squaring (114) a limited precision square root of the reciprocal (112). A final reciprocal is computed using a finite power series (104). Finally, modified numerators are formed (106) by biasing the original numerators, products of the modified numerators multiplied times the reciprocal are computed, and the products are rounded up or down as required (108).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.