Shift-register based row select circuit with redundancy for a FIFO memory
US5768196A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 1, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Mar 1, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO (First-In-First-Out) memory includes a main memory array and a main select circuit having a plurality of serially coupled shift registers, each selecting at least one memory location of the main memory array. The FIFO memory also includes a redundant memory array and a redundant select circuit having a plurality of redundant shift registers, each selecting at least one redundant memory location of the redundant memory array. A switching circuit is provided in the FIFO memory that is coupled to each of the shift registers and each of the redundant shift registers. When a memory location of the main memory is found defective, the switching circuit causes a corresponding shift register of the shift registers to be bypassed in the main select circuit and a redundant shift register of the redundant shift registers to be serially coupled into the main select circuit via a last one of the shift registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.