Method and apparatus for priority level queueing in processing ATM cell header and payload
US5768273A · kind A · utility
13Cited by
6References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 1, 1995 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Nov 1, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/3009
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An ATM switch includes one or more adapters having input ports and/or output ports and a switching fabric for switching Asynchronous Transfer Mode (ATM) cells received at the input ports to the output ports. To maintain switch throughput, cells are categorized either as real time (high priority) or non-real time (lower priority) cells. High priority cells are processed using a first set of cell processing logic at a rate at least equal to the rate at which the cells are received on the input ports. Lower priority cells are processed using a second set of cell processing logic only when no high priority cells are being processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.