Digital phase adjustment circuit for asynchronous transfer mode and like data formats
US5768283A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 8, 1994 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Nov 8, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5674
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase adjustment circuit adjusts the phase between cell signals and a start-of-cell marker. The circuit relies on a known data pattern in unassigned cell signals in order to determine the phase. During a learning mode, the circuit samples an unassigned cell signal several times during a selected cell time to determine the location of the known data pattern. If the data pattern is not at the sampled position, the circuit increments the cell time during which it samples the next unassigned cell signal by one period, and decreases an amount of delay the circuit provides to a selected sample signal by one clock period. In this manner, the circuit can compensate for up to about two periods of delay before sampling the known data pattern. Thereafter, the circuit enters a tracking mode, and tracks phase variations between the cell signals and the start-of-cell marker. Additionally, the circuit selects a sample output signal which replicates the cell signals but is not subject to metastability. The skewed clocks are generated from a delay line having a number of variable delay elements. A circuit determines how many delay elements are needed to delay an input clock by one period,…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.