Mixing circuit utilizing N inputs and a number of decimation filters that is less than N
US5768316A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 29, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Feb 29, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/1647
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A mixing circuit for synthesizing plural .DELTA..SIGMA. modulated data generated simultaneously with a bit rate F to single mixed data includes a slot determining section for dividing time length corresponding to 1-bit period of the .DELTA..SIGMA. modulated data into a number N which is of the same number as the plural .DELTA..SIGMA. modulated data, and a time division multiplex section for assigning in order the plural .DELTA..SIGMA. modulated data to the 1-bit period at a bit rate N*F on a time shared basis. The obtained mixed data can be converted to linear PCM data with a single decimation circuit. By increasing the bit rate of the mixed data by N times the bit rate F of the .DELTA..SIGMA. modulated data, a total gain can be maintained at a constant value irrespective of a change in the number of data to be synthesized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.