Time-adjustable delay circuit
US5768325A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 1996 |
| Grant date | Jun 16, 1998 |
| Priority date | — |
| Expiry date | Jan 25, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/062
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A delay circuit externally adjustable for the delay time "n" as desired, which comprises a FIFO (FIRST-IN, FIRST-OUT) type memory, a self-load counter, and a decoder circuit. In addition to a data signal, an input clock is inputted to the memory as the write clock and the read clock. The self-load counter operates in synchronization with the input clock, and loads a setting of a load value-designating signal at a prescribed number of counts. The decoder circuit receives the output of the self-load counter which has a prescribed cycle, and outputs a reset signal with the same cycle to the memory. This cycle determines the delay time. The delay circuit allows a greatly reduced number of ICs used as compared with the prior art, even for increased delay times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.