Method for forming an inductor devices using substrate biasing technique
US5770509A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 1997 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Apr 22, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01F2017/0046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Methods for foming an inductor devices used for impedance matching in the radio frequency integrated circuits are disclosed. In the integrated inductor device according to the present invention, an additional electrode is arranged in surroundings of an inductor metal line, and the reverse bias voltage is applied to the region between the substrate and the electrode so as to form a depletion layer. Therefore, the substrate biasing is effected and thus an inductor having improved performance can be formed by decreasing the parasitic capacitance between the inductor metal line and the substrate. The present invention can also be applied to another semiconductor device having metal lines and pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.