Integrated chip package with reduced dimensions and leads exposed from the top and bottom of the package
US5770888A · kind A · utility
226Cited by
9References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1996 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Aug 23, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved package is thinner with increased memory capacity and improved heat emission effect. The package includes a plurality of leads, where each lead comprises a first connection lead and a second connection lead with upper and lower surfaces. An integrated chip, such as a semiconductor chip, is attached to a portion of the upper surface of the first connection lead. The chip and leads are molded such that the lower surface of the first connection leads and upper surface of the second connection leads are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.