Bit-serial digital compressor
US5771182A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 31, 1996 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | May 31, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/30
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A bit-serial compressor (106) has a pre-divider circuit (208) receiving input serial data and generating a partial numerator. Divider circuit (210) divides the partial numerator by a denominator and generates a partial remainder that is fed back to the pre-divider circuit (208). Divider circuit (210) also generates serial data that is sent to an absolute value circuit (216) and then to a bit-serial filter (218). Bit-serial filter (218) generates an average signal from the serial data. A comparator circuit (224) compares the average signal to a threshold signal and generates the greater of the average signal or the threshold signal for use as a denominator in a next division cycle. The divider circuit includes an overflow control circuit (618) which detects overflow from the carryout bit of the partial remainder operation at the beginning of a division cycle and the sign bit of the numerator. If overflow is detected, the output is clipped according to whether the numerator is positive or negative.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.