Apparatus for delaying the output of data onto a system bus
US5771372A · kind A · utility
4Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1995 |
| Grant date | Jun 23, 1998 |
| Priority date | — |
| Expiry date | Oct 3, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.