Computer program product for enabling a computer to remove redundancies using quasi algebraic methods
US5774369A · kind A · utility
12Cited by
9References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 6, 1995 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Jun 6, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.