PVT self aligning internal delay line and method of operation
US5774403A · kind A · utility
38Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 12, 1997 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Jun 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit process, voltage and temperature fluctuation self-aligning internal delay line circuit and method of operation. A PVT related reference signal is compared to a set of reference signals generated from a system voltage. A delay line is varied based upon the comparison results, generating a delayed timing signal related to PVT fluctuations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.