Method and apparatus for emulating status flag
US5774694A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1996 |
| Grant date | Jun 30, 1998 |
| Priority date | — |
| Expiry date | Sep 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30174
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for emulating status flags on a computer system that has no native support for status flags. One embodiment of the invention includes decoding an arithmetic instruction executable on a first Instruction Set Architecture (ISA), wherein the instructions generates at least one status flag when executed on the first ISA. The arithmetic instruction is translated to be executable on a second ISA. When executed on the second ISA, the translated arithmetic instruction generates a first intermediate result by performing a first logical exclusive-or (XOR) operation between a first operand and a second operand. The arithmetic instruction then generates a first final result by performing a second XOR operation between the first intermediate result and an arithmetic result, which was generated by an arithmetic operation specified by the arithmetic instruction. As a result, the first final result has at least one bit representing a status flag of the arithmetic result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.