Fabrication method for high-capacitance storage node structures
US5776660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Feb 3, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/24628
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A high capacitance storage node structure is created in a substrate by patterning a hybrid resist (12) to produce both negative tone (16) and positive tone (18) areas in the exposed region (14). After removal of the positive tone areas (18), the substrate (12) is etched using the unexposed hybrid resist (12) and negative tone area (16) as a mask. This produces a trench (22) in the substrate (12) with a centrally located, upwardly projecting protrusion (24). The capacitor (26) is then created by coating the sidewalls of the trench (22) and protrusion (24) with dielectric (28) and filling the trench with conductive material (30) such as polysilicon.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.