Method for fabricating a triple well for bicmos devices

US5776807A · kind A · utility

Assignee

• Tritech Microelectronics, Ltd · SG

Inventors

• Hannu O. Ronkainen · Hyrynsalmi, FI
• Gao Minghui · Singapore, SG

Key dates

• Filing date: Aug 13, 1997
• Grant date: Jul 7, 1998
• Expiry date: Aug 13, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0109

Abstract

To accomplish the above objectives, the present invention provides a method of fabricating a collector well in a semiconductor BiCMOS device. The method begins by providing a substrate having c-well areas, N-well areas, and P-well areas. The substrate has n-plug doped regions in said c-well areas. A stress release oxide layer is grown over the substrate surface. A first nitride layer 27 is formed over the stress release oxide layer 26. A C-well mask 29having C-well mask openings 28A is formed over C-well areas 28 and openings are formed in the first nitride layer. Impurities are implanted through the opening forming collector-well regions. The c-well mask is then removed. A n-well photoresist mask having n-well mask openings 42A is formed over the first nitride layer and openings are etched in the first nitride layer over N-well areas 40. Ions impurities are implanted through the n-well nitride opening 42A forming n-well regions 44 in the n-well area in the substrate 10. The n-well mask 42 is then removed. A triple well oxide layer 45, 46 is formed over the n-well region 44, the c-well region and the n plug regions. The first nitride layer is then removed. Ion impurities into the s…