Circuit for preventing more than one transistor from conducting
US5777496A · kind A · utility
6Cited by
24References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 27, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Mar 27, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A totem pole output stage including first and second control modules cross coupled to first and second switching modules for measuring the charge on the gate of a FET contained in the opposing switching module to determine the condition of the opposing switching module, so as to avoid mutual conductivity events without the use of a fixed timing delay while maximizing switching performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.