Data demodulation apparatus
US5777511A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Apr 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04H2201/13
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital modulating signal, which is a binary conversion of an RDS signal by a comparator, is sampled by a D-FF with a regeneration clock synchronized with a carrier regenerated by a carrier regeneration circuit. Next, a comparator output is input by an edge detection circuit where a data edge is detected, and the edge interval between this edge and the sampling timing edge of the regeneration clock is detected by a reliability judgment circuit where the edge interval is encoded and output as reliability data. Then, the reliability data is added as LSB data to various sampling data, and data for various symbols is regenerated at the data regeneration circuit. This minimizes the influence of the error data on the data regeneration circuit even if data is sampled erroneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.