FPGA redundancy
US5777887A · kind A · utility
45Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1995 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | May 12, 2015 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17764
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An FPGA includes primary resources and redundant resources. To program an FPGA to perform a desired function, a pattern of programmable elements to be programmed that takes advantage of primary resources only is first prepared. This pattern is then modified responsive to previously obtained information about defects within the FPGA. The modified pattern takes advantage of redundant resources as direct or indirect substitutes for FPGA elements rendered unusable by defects. The FPGA is programmed in accordance with the modified pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.