Memory device with fast write recovery and related write recovery method
US5777935A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 1997 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Mar 12, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory (10) such as a current sensing static random access memory (SRAM) achieves fast write recovery through bit line loads and two additional mechanisms. First, an additional load (252) on shared data lines also becomes active to speed the write recovery process. Second, multiple columns (200, 202, 204) are connected to common data lines during write recovery so that a column written to during a write cycle may be again precharged in part by charge sharing using the charge stored in other columns. These two mechanisms allow fast write recovery with minimum column pitch and avoid the problems which would be encountered if the loads were placed on the write data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.