Clock and counter for bit cell determination and timeout timing for serial data signaling on an apple desktop bus
US5778201A · kind A · utility
Inventor
Key dates
| Filing date | Jan 26, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Jan 26, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4286
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for bit cell determination and timeout detection for an Apple Desktop Bus, using a counter clocked by a clock generator, according to the steps of: At the start of a bit cell, loading an initial value into the counter and enabling the counter to count down as clocked by the clock generator. Counting down until a low to high transition in the input ADB signal is detected or a terminal count is reached, such that if the low to high transition transition is detected, then enabling the counter to count up, else if the terminal count is reached, then indicating a timeout condition. If the counter is enabled to count up, then counting up until a high to low transition in the input ADB signal is detected or the terminal count is reached, such that if the high to low transition is detected, then stopping the counter and reading a final value to determine the bit cell value, else if the terminal count is reached, then indicating a timeout condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.