Parallel signal processing device for high-speed timing
US5778217A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1996 |
| Grant date | Jul 7, 1998 |
| Priority date | — |
| Expiry date | Apr 2, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel signal processing device for high speed timing recovery in a high speed transfer network includes a plurality of data sampling processors (DSP), a central phase-error processor (CPP), and a recovered clock phase adjuster (RCPA. The sampling of transfer data, processing of sampling data, and adjustment of the recovered clock are executed by a plurality of data sampling processors for producing phase difference signals which are then transferred separately to a central phase-error processor. Phase-error adjustment signals for each data sampling processor are produced by the central phase-error processor, and the recovered clock phase for each data sampling processor is adjusted by the recovered clock phase adjuster according to the phase-error. Because the data sampling, phase processing, and adjustment of the recovered clock are simultaneously and parallelly processed by each set of data sampling processors, the high speed recovered clock is readily updated and the data is correctly read by the receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.